1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device, which has a long refresh cycle, and can accurately amplify data read from a memory cell.
2. Description of the Background Art
For providing an on-chip large-scale memory in a system LSI (Large Scale Integration), it is necessary to fabricate a memory portion by a CMOS (Complementary MOS) logic process for suppressing increase in cost and preventing lowering of a performance of a logic circuit.
An SRAM (Static Random Access Memory) is a kind of memory, which can be fabricated by the CMOS logic process. However, various problems arise if the capacity of the SRAM is increased.
First, if the SRAM employs memory cells formed of the CMOS, one memory cell requires six transistors, and therefore occupies a large area. Therefore, increase in capacity results in increase in area of the whole system chip, and therefore results in increase in cost and lowering of yield.
As a result of miniaturization in the CMOS process, a non-negligible off-leakage current occurs in the transistors of the memory cell, and standby current unavoidably increases.
In view of the above problems, a planar DRAM (Dynamic Random Access Memory), which can be fabricated by the CMOS logic process, may be used. The planar DRAM has a smaller area than the SRAM, and periodically requires a smaller refresh current so that the standby current can be smaller than that of the SRAM, and thus the planar DRAM is very useful.
Referring to FIG. 17, a memory cell 200 in a planar DRAM is formed of P-channel MOS transistors 201 and 202. P-channel MOS transistor 201 is connected between a bit line BLi (i: natural number satisfying (0xe2x89xa6ixe2x89xa6m), where m is a natural number) and a node NS. P-channel MOS transistor 201 has a gate terminal connected to a word line WLj (j: natural number satisfying (0xe2x89xa6jxe2x89xa6n), where n is a natural number).
P-channel MOS transistor 202 has source and drain terminals connected to a node NS, and receives on its gate terminal a cell plate voltage VCP formed of a ground voltage GND.
Word line WLj carries a power supply voltage Vcc during standby, and carries ground voltage GND when it is active.
When word line WLj is active, P-channel MOS transistor 201 is on so that data is sent to or from a channel region (i.e., node NS) of P-channel MOS transistor 202 via P-channel MOS transistor 201.
FIG. 18 shows a layout of memory cells of a planar DRAM. Referring to FIG. 18, active regions 203 and 204 are formed on a deeper side of a sheet of FIG. 18. A cell plate 205 and word lines WLjxe2x88x921 and WLj are formed on active region 203. A cell plate 206 is formed over both active regions 203 and 204, and a cell plate 207 and word lines WLj+1 and WLj+2 are formed on active region 204. A bit line pair BLi and /BLi is formed in a direction perpendicular to word lines WLjxe2x88x921-WLj+2. A contact 208 is formed between word lines WLjxe2x88x921 and WLj for connecting bit line BLi to a source terminal of a transistor formed under word line WLj. Also, a contact 209 is formed between word lines WLj+1 and WLj+2 for connecting bit line /BLi to a source terminal of a transistor formed under word line WLj+1.
FIG. 19 is a cross section of a region 210 shown in FIG. 18. Referring to FIG. 19, an N-well 221 is formed at a surface layer of a p-type silicon substrate 220. P+diffusion layers 222 and 223 are formed at portions of N-well 221. A gate 224 is formed on N-well 221 located between P+diffusion layers 222 and 223. Word line WLj is formed on gate 224.
A gate 225 is formed on N-well 221 neighboring to P+diffusion layer 223, and a cell plate 204 is formed on gate 225. Contact 208 is formed on P+diffusion layer 222, and connects bit line BLi to P+diffusion layer 222. Insulating portion 208A is formed at N-well 221 of the region neighboring to gate 225. Insulating portion 208A is used for element isolation.
P+diffusion layers 222 and 223 as well as gate 224 form P-channel MOS transistor 201, and P+diffusion layers 223 and gate 225 form P-channel MOS transistor 202.
Cell plate 204 is supplied with cell plate voltage VCP formed of ground voltage GND. Therefore, an inverted layer 226 is formed at the surface of N-well 221 under cell plate 204 when positive charges are accumulated as a result of writing of H-data.
Referring to FIG. 20, an operation of writing H-data will now be described. The xe2x80x9cH-dataxe2x80x9d means data written with a high voltage. When the voltage on word line WLj lowers from power supply voltage Vcc to ground voltage GND, word line WLj becomes active so that P-channel MOS transistor 201 is turned on. Positive charges forming the H-data on bit line BLi flow through P+diffusion layer 222 and the channel region into P+diffusion layer 223. Since ground voltage GND is placed on cell plate 204, a sufficient potential difference is present between P+diffusion layer 223 and cell plate 204 so that a large amount of positive charges flow from P+diffusion layer 223 into the channel region of P-channel MOS transistor 202. Consequently, inverted layer 226 is formed at the channel region of P-channel MOS transistor 202. Therefore, the H-data can be easily written into the memory cell of the planar type. When the H-data is written into the memory cell, the memory cell has a large cell capacity.
Referring to FIG. 21, an operation of writing L-data will now be described. The xe2x80x9cL-dataxe2x80x9d means data written with a low voltage. When the voltage on word line WLj lowers from power supply voltage Vcc to ground voltage GND, word line WLj becomes active so that P-channel MOS transistor 201 is turned on. Negative charges forming the L-data on bit line BLi flow through contact 208 into P+diffusion layer 222. The negative charges in P+diffusion layer 222 do not sufficiently flow into P+diffusion layer 223 through the channel region of P-channel MOS transistor 201 due to a threshold loss in P-channel MOS transistor 201. Since the voltage placed on cell plate 204 is ground voltage GND, a sufficient potential difference does not occur between P+diffusion layer 223 and cell plate 204, and an amount of negative charges flowing from P+diffusion layer 223 into the channel region of P-channel MOS transistor 202 is small. Consequently, inverted layer 226 is not formed at the surface of N-well 221 under cell plate 204. As described above, the cell capacity of the memory cell carrying the L-data is very small.
Description will now be given on an operation of reading data from the memory cell of the planar type. Immediately before the read operation, bit line pair BLi and /BLi is precharged to carry a precharge voltage Vcc/2. When the voltage on word line WLj lowers from power supply voltage Vcc to ground voltage GND, word line WLj becomes active so that P-channel MOS transistor 201 is turned on. The charges held in P-channel MOS transistor 202 flow to bit line BLi through P-channel MOS transistor 201 and contact 208, and the voltage on bit line BLi slightly changes from precharge voltage Vcc/2 in accordance with the logical level of read data.
More specifically, the voltage on bit line BLi changes from precharge voltage Vcc/2 to a voltage of (Vcc/2+xcex94V) when the memory cell has stored H-data. When the memory cell has stored L-data, the voltage on bit line BLi changes from precharge voltage Vcc/2 to a voltage of (Vcc/2xe2x88x92xcex94V).
The data read onto bit line BLi is amplified by a sense amplifier SA. Referring to FIG. 22, sense amplifier SA includes P-channel MOS transistors 227-229 and N-channel MOS transistors 230-232. P-channel MOS transistor 227 is connected between a power supply node NVC and a node N5. P-channel MOS transistor 227 receives on its gate a signal /SOP.
P-channel MOS transistor 228 and N-channel MOS transistor 230 are connected in series between nodes N5 and N8. P- and N-channel MOS transistors 229 and 231 are connected in series between nodes N5 and N8. P- and N-channel MOS transistors 228 and 230 are connected in parallel to P- and N-channel MOS transistors 229 and 231.
P- and N-channel MOS transistors 228 and 230 receive on their gate terminals a voltage placed on a node N7. P- and N-channel MOS transistors 229 and 231 receive on their gate terminals a voltage placed on a node N6.
N-channel MOS transistor 232 is connected between node N8 and ground node GND. N-channel MOS transistor 232 receives a signal SON on its gate terminal. Bit line BLi is connected to node N6 located between P- and N-channel MOS transistors 228 and 230. Bit line /BLi is connected to node N7 located between P- and N-channel MOS transistors 229 and 231.
Sense amplifier SA becomes active when it receives signal /SOP at L-level and signal SON at H-level.
Referring to FIG. 23, description will now be given on an operation of sense amplifier SA. Before reading the data from the memory cell, bit line pair BLi and /BLi is precharged to carry precharge voltage Vcc/2. When the voltage on word line WLj lowers from power supply voltage Vcc to ground voltage GND, word line WLj becomes active so that the H-data is read from the memory cell onto bit line BLi. The voltage on bit line BLi changes from precharge voltage Vcc/2 to a voltage of (Vcc/2+xcex94V). In this case, the voltage on bit line /BLi remains at precharge voltage Vcc/2.
In sense amplifier SA, P- and N-channel MOS transistors 229 and 231 receive the voltage of (Vcc/2+xcex94V) on their gate terminals, and P- and N-channel MOS transistors 228 and 230 receive precharge voltage Vcc/2 on their gate terminals.
Since P-channel MOS transistor 228 receives on its gate terminal a voltage lower than that received by P-channel MOS transistor 229, P-channel MOS transistor 228 is turned on, and the voltage on node N6 rises from the voltage of (Vcc/2+xcex94V) to power supply voltage Vcc. Thereby, P-channel MOS transistor 229 is turned off, and N-channel MOS transistor 231 is turned on so that the voltage on node N7 lowers from precharge voltage Vcc/2 to ground voltage GND. N-channel MOS transistor 230 is turned off.
In this manner, sense amplifier SA raises the voltage on bit line BLi from voltage (Vcc/2+xcex94V) to power supply voltage Vcc, and lowers the voltage on bit line /BLi from precharge voltage Vcc/2 to ground voltage GND. Thus, sense amplifier SA amplifies the H-data read onto bit line BLi.
When L-data is read from the memory cell onto bit line BLi, the voltage on bit line BLi changes from precharge voltage Vcc/2 to the voltage of (Vcc/2xe2x88x92xcex94V). In this case, the voltage on bit line /BLi remains at precharge voltage Vcc/2.
In sense amplifier SA, P- and N-channel MOS transistors 229 and 231 receive the voltage of (Vcc/2xe2x88x92xcex94V) on their gate terminals, and P- and N-channel MOS transistors 228 and 230 receive precharge voltage Vcc/2 on their gate terminals.
Since P-channel MOS transistor 229 receives on its gate terminal the voltage lower than that received by P-channel MOS transistor 228, P-channel MOS transistor 229 is turned on, and the voltage on node N7 rises from precharge voltage Vcc/2 to power supply voltage Vcc. Thereby, P-channel MOS transistor 228 is turned off, and N-channel MOS transistor 230 is turned on so that the voltage on node N6 lowers from the voltage of (Vcc/2xe2x88x92xcex94V) to ground voltage GND. N-channel MOS transistor 231 is turned off.
As described above, sense amplifier SA lowers the voltage on bit line BLi from the voltage of (Vcc/2xe2x88x92xcex94V) to ground voltage GND, and raises the voltage on bit line /BLi from precharge voltage Vcc/2 to power supply voltage Vcc. Thus, sense amplifier SA amplifies the L-data read onto bit line BLi.
As described above, the data read from the memory cell of the planar type is amplified by sense amplifier SA.
However, the sense amplifier SA can amplify the read data only in such a case that a potential difference, which can be amplified by sense amplifier SA, occurs between bit lines BLi and /BLi when the data is read from the memory cell onto bit line BLi or /BLi. Thus, the sense amplifier SA can amplify the read data only when the memory cell holds the charges corresponding to the written data.
As described above, the H-data can be easily written into the memory cell of the planar type, and the memory cell holding the H-data has a large cell capacity. Therefore, when the H-data is read from the memory cell, a potential difference xcex94V0, which can be amplified by sense amplifier SA, occurs between bit lines BLi and /BLi as illustrated in FIG. 24.
However, it is difficult to write the L-data into the memory cell of the planar type, and the cell capacity is small in the memory cell holding the L-data. Therefore, when the L-data is read from the memory cell, a potential difference xcex94V2, which cannot be amplified by sense amplifier SA without difficulty, occurs between bit lines BLi and /BLi, as illustrated in FIG. 25. Thus, a potential difference required for a reliable sense operation cannot be produced when the L-data is written in the memory cell of the conventional planar type.
For writing the L-data into the memory cell of the planar type so that a potential difference required for the reliable sense operation may be produced, the voltage applied to gate 224 of P-channel MOS transistor 201 must be set to xe2x88x920.4 V (nearly equal to the threshold voltage of P-channel MOS transistor 201) lower than ground voltage GND of 0 V, and the voltage of xe2x88x920.4 V must be applied also to cell plate 204.
However, the voltage (xe2x88x920.4 V) lower than the ground voltage GND of the silicon substrate cannot be used in the twin well structure without difficulty, and also increases power consumption.
Therefore, the memory cell of the conventional planar type suffers from such a problem that the potential difference required for the reliable sense operation cannot be obtained easily.
The memory cell of the planar type holds information based on the amount of charges, but the amount of accumulated charges decreases due to a leak current with time. Referring to FIG. 26, a gate leak current 233 is most dominant among leaks currents, and a junction leak current 234 is secondarily dominant.
Gate leak current 233 occurs due to the fact that a gate oxide film forming gate 225 is thin. Gate leak current 233 flows when charges leak from P+diffusion layer 223 forming the storage node to cell plate 204. Therefore, when P+diffusion layer 223 accumulates the charges corresponding to the H-data, gate leak current 233 becomes remarkable.
The junction leak current 234 is a reverse-direction junction current occurring between N-well 221 under the memory cell and P+diffusion layer 223 forming the storage node. Junction leak current 234 becomes particularly remarkable when P+diffusion layer 223 accumulates the charges corresponding to the L-data.
Accordingly, the potential on P+diffusion layer 223 forming the storage node changes as illustrated in FIG. 27. When the H-data is written into the memory cell, P+diffusion layer 223 initially carries a sufficiently high potential of power supply voltage Vcc. As the time elapses, gate leak current 233 occurs, and the potential on P+diffusion layer 223 rapidly lowers.
When the L-data is written into the memory cell, P+diffusion layer 223 initially carries a potential Vthp raised by threshold voltage Vthp of P-channel MOS transistor 201. Thereafter, a junction leak current 234 occurs as the time elapses so that the potential on P+diffusion layer 223 rises. When the potential on P+diffusion layer 223 rises to a certain extent, gate leak current 233 increases so that the rising of the potential stops.
In the memory cell of the planar type, as described above, gate leak current 233 is large, and the data holding time depends on the degree of deterioration of H-data so that the refresh operation must be performed frequently, resulting in increase in power consumption.
Accordingly, an object of the invention is to provide a semiconductor memory device, which can operate with a long refresh cycle, and can accurately amplify data read from a memory cell.
According to the invention, a semiconductor memory device includes a plurality of memory cells and a peripheral circuit. The plurality of memory cells are arranged in rows and columns. The peripheral circuit can provide data into and from each of the plurality of memory cells.
Each of the plurality of memory cells includes a capacity element for storing the data, and the capacity element is formed of first and second elements. The first and second elements accumulate charges corresponding to first write data and second write data different from said first write data, respectively.
According to the invention, therefore, a sufficient potential difference can be produced on a bit line pair in both the cases where first data is read from the memory cell, and where second data is read therefrom.
Further, the data holding time of the memory cell can be significantly longer than that of a memory cell of a conventional planar type, and the number of refresh operations per time can be significantly reduced. This can significantly reduce power consumption.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.